Global Research Alliance: A new breakthrough in 5nm new transistor technology

IBM senior researcher Nicolas Loubet holds a 5nm thick silicon crystal chip that improves performance by about 40% at fixed power and 75% energy at matched performance.

IBM and its research alliance partners Grofund, Samsung and related suppliers have recently developed a new type of nano-flake silicon transistor with a thickness of only 5 nm. Details of the study will be disclosed at the 2017 Tokyo Symposium on SLSI Technology and Circuits. In just two years after the 7nm thick node chip was developed, scientists have once again broken through new technologies and developed 30 billion switch-switched 5nm chips.
This technology will greatly improve the performance of intelligent computing, IoT and data-intensive devices; and the energy efficiency will greatly increase the battery life of smartphones and other mobile devices by two to three times.
Scientists have replaced the FinFET structure (standard fin field effect transistor) with stacked silicon nanosheets as a transistor device structure. The FinFET structure was previously a blueprint for 7nm thin chip technology.
The future economic and social development has great demand for intelligent computing and cloud computing, and the innovation and promotion of semiconductor technology play an important role in it. Arvind Krishna, senior vice president and head of the IBM research group, said: Based on the requirements and promotion of this big environment, IBM is actively exploring new and unique structural technologies and new materials to promote innovation in the semiconductor industry.

In the laboratory of the State University of New York Institute of Technology, IBM researchers used 5nm silicon wafer transistors to prepare test wafers and load them into front-end open wafer transfer boxes.

The study, published in the journal VLSI entitled "Stacked Nanoflake Circumpolar Grids", demonstrates that the preparation of 5nm wafers is feasible and more efficient; it will be applied in practice in the near future.
Compared with the current 10nm mainstream technology on the market, the 5nm size thin film technology can enhance 40% performance under fixed power conditions, and can save 75% energy under matching performance conditions. This technology greatly caters to the future development requirements of artificial intelligence systems, virtual reality and mobile devices.

The IBM research team used nano-silicon wafer stacking technology as the device structure to fabricate an electronic scan of a 5 nm transistor, enabling 30 billion units of switches on a fingernail-sized wafer for more efficient transmission and higher performance.

The IBM team has been working on thin-film semiconductors for more than 10 years. This research is the first in the industry to design and fabricate stacked nanosheet devices with superior electronic performance over traditional FinFET structures.
The nanoflake transistor structure in this study uses Far Ultraviolet Lithography (EUV), which enables continuous adjustment of nanosheet widths, either within a single manufacturing process or within the wafer design flow. This tunability technique can fine-tune the performance and power of a particular circuit, which is not currently available in FinFET transistor fabrication processes, and it is the current-loading scale of FinFET transistors that limits the breakthrough and development of the process. Therefore, even if the FinFET wafer can achieve a size of 5 nm, simply shrinking the space between the scales does not effectively increase the current and provides an additional performance improvement. ( Compile: China Superhard Materials Network )